View LZ9GF16_252952.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SHARP
ISPEC No. ISSUE: 1 To : ED1 Sep. 2 1999
SPECIFICATIONS.
Product Type
LZ 9 G
Series
1600
Gates
Gate
Array
Model No.
LZ9GFl6
contains 22
please
-X This specifications
If
pages including
contact us before
the cover and appendix.
issuing purchasing order.
you have any objections,
CUSTOMERS ACCEPTANCE DATE : BY: __-__--_--.PRESENTED
Dept.General Manager REVIEWED BY: PREPARED BY:
Engineering Dept. 2 Display Device System LSI Development Center Integrated Circuits Group SHARi CORPORATION -
SHARP
LZ9GF16
@Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. @Whenusing the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. ( 1 ) The products covered herein are designed and manufactured for the following application areas. Whenusing the products covered herein for the equipment listed in Paragraph (2 1, even for the following application areas, be sure to observe the precautions given in Paragraph ( 2 ). Never use the products for the equipment listed in Paragraph ( 3 ). *Office electronics . Instrumentation and measuring equipment Machine tools * Audiovisual equipment Home appliances * Communication equipment other than for trunk lines
l l
( 2 > Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. . Control and safety devices for airplanes, trains, automobiles, and other transportation equipment . Mainframe computers . Traffic control systems . Gas leak detectors and automatic cutoff devices 0Rescue and security equipment 0 Other safety devices and safety equipment, etc. ( 3 ) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment * Communications equipment for trunk lines . ControI equipment for the nuclear power industry *Medical equipment related to life support, etc. ( 4 )Please direct all queries and comments regarding the interpretation to a sales representative of the company. of the above three Paragraphs
l Please direct all queries regarding the products covered herein to a sales representative company.
of the
LZ9GFi6
1
CONTENTS Page . . . . 02
. .
.
1. Introduction 2. Feature 3. Pin Assignments 4. Explanation of Input / Output signal 5. Absolute Maximum Ratings 6. Electrical Specifications
.. ..
. .
. .
.
92 l3
l
4-5
... ... . .
. .
-6 -6
l
7. Condition for signal circuit 8. Illustration of control circuit
.. .. .. ..
7-8 9-11
.. .. ..
l
9. Input / Output signal timing chart for above cases 10. OutIine dimension
' 12-19
l
20
* SHARI=
1. Introduction
.
LZ9GF16
2
This data sheet is to introduce the specification of LZ9GF16, timing control IC for TFT-LCDmodule. The functions and the uses Timing control IC for 5" size and 5.6" size TFTlLCDmodule Horizontal frequency driver(NTSC:600 divided frequency /PAL:604 divided frequency) and phase comparator circuit for the PLL circuit are built in. By adding voltage Controlled Oscillator(VC0) and Low Pass Filter(LPF) to this IC to make the PLL circuit, following signals synchronized with input composite sync. Signal(SYN1) and vertical sync. Signal(VIN) conforming to NTSC PAL are generated. or 1) 2) 3) 4) 5) 6) 7) 8) Driving Control Driving Control Control Polarity Polarity Control signal for source driver signal for source driver signal for gate driver signal for gate driver signal for gate driver power supply making alternating signal for common electrode driving signal alternating signal for video signal signal for the backlight PWM brightness control : : : : : : : : CLD, SPD CTR, DIS CLS, SPS LOW0 GPS FBPT FRPV CHK
Illustration of control circuit Input/Output signal timing chart for above cases
: See fig. l-a - l-c : See fig. 2-a - 2-j
2. Feature : CMOS Process : P-type silicon substrate Wafer substrate (0.75mmpin pitch) (pin & type) : 48QFP Package (material) : Plastics Operating Temperature : -30C - +85"C : 0. Snslgate Propagation delay time (Condition : Z-input NAND,Fanout=X, wire length=2mm, supply voltage=5V, Operating temperature Topr=25"C) *REMARK Not designed or rated as radiation hardened. You cannot rewrite the program.
SHARP
3. Pin Assignment
LZ9GF16
3
ICU ICS 01M 02M ORZ ORZx2 TOlM IOCUBM IOCURZ OSCB osco
hD
: : : : : : * : : : : : : :
GND
Input buffer CMOS level with PULLUPresistance R=250k8 Schmitt-trigger Input buffer CMOS level Output buffer I,=O.BmA Output buffer 1,,=1.61nA I,,=BOfiA Slew rate controlled Output buffer Slew rate controlled Output buffer 1~,=16OflA . ORZx2 buffer is connected two ORZbuffer in parallel. Tri-state Output buffer 1,,,=0.8mA Bidirecional buffer CMOS level with PULLUP resistance R=250kQ, 1,~=1.6mA Slew rate controlled Bidirecional buffer CMOS level with PULLUP resistance R=250kQ, IoL=80pA 10,=3. 2mA Oscillator Bidirecional buffer with oscillation stop control Oscillator Output buffer Io,=l.6mA Power supply pin Earth pin
SHARP
4. Explanation of Input / Output signal
?IN No.'
LZ9GF16
4
1
.
1 2 3 4 5 6 7
a
I
9 10 11 12 13 14 15 16 17
ia
19
20 21 22 23 24 25 26 27 28
Signal Name VIN CVOP CVIN DVOP FBJT GPS GND EXCL SYNI HSY VSY DIS TEST0 NTPC VRVC HRVC CHK TEST1 TEST0 IVB SPS CLS LOW0 CT& SPD CLD
osco
Explanation
I/O
I 0 I 0 0 0 I/O I I/O I/O 0 0 I I I 0 I 0 0 0 0 0 0 /0 / _.I
,
29
30
I
j
oscI SAM0
bD
31 / GND 32 I TEST1 -__ 7---./Input-f;;-ini 1--33 LOW1 -L--I .---__ --F-~~--~-`--.-..-__34 IPoIarlty alternatingVertical sync. Signal input (Positive) Vertical sync. Signal Output for Count Downcircuit Vertical sync. Signal input for Count Downcircuit Vertical sync. Signal output for digital separator circuit (Positive) Polarity alternating signal output for commonelectrode driving signal Logic pals output for gate driver power supply making Ground Input / Output for outside Clock signal Composite sync. signal input Internal horizontal sync. signal output (Negative) Internal vertical sync. signal output (Negative) Control signal output for source driver Monitor signal output for test Terminal for display mode change NTSCor PAL [Note11 Input for the Vertical scanning direction setting (Note21 Input for the horizontal scanning direction setting (Note31 Output for signal of backlight brightness control Input terminal for test (Note41 Monitor signal output for test Scanning setting input for gate driver _-Besetting signal output for gate driver Clock signal output for gate driver .__. Control signal output for gate driver Control--__ signal _____- for source driver output Starting signal output for source driver Clock signal output for source driver __--__.Output _---_ clock oscillator circuit for .--Input clock oscillator circuit -____ ..___- for --._-..._--.- ___Control signal --.. ~__ for source driver output ~----t---------.~... IPower supply voltage _ ._ ..-. -~- -- -..__--__ ~-______ IGround f--------;. _- ---- --__ IInput terminal fil forye;;7-;j-ga1 test(Note41 ~~~--~
SHARF=
(Note11 (Note21 [Note31 NTPH=H NTPC=L VRVC=H VRVC=L HRVC=H HRVC=L Normal state BESH=H RESH=L RESV=H RESV=L CLOC=H CLOC=L CLKC=H CLKC=L SAMC=H SAMC=L
.
LZ9GF16
5
: NTSCnethod : MBK-PAL method : Normally (Positive scanning) : Reversal (Negative scanning) : Normally (Positive scanning) : Reversal (Negative scanning) (Refer : 9, Scanning direction setting) : H level : Normally : forcible reset : Normally : forcible reset : L level output : H level output : EXCL, HSY, VSYterminals becomeoutput mode : EXCL, HSY, VSYterminals becomeinput mode : It is the independent data-sampling timing at RGB : It is the simultaneous data-sampling timing at RGB dots
(Note41 (Note51 [Note61 (Note71 (Note81 (Note91 (Note101
Horizontal display position is changed by delay time
SHARI=
5. Absolute Maximum Ratings
Parameter Supply voltage
InDut V"'+a-
LZ9GF16
6
Symbo 1
VDD V,
Output vo 1tage IOerating temperature ptorage temperature
I "0 I 1 Topr 1 1 Tstg 1
Rating -0.3~t6.0 -0.3~vnrl+0.3 -u..J- VDDTU. J -3o--+85 -55-t150
Unit V V "C
6. Electrical Specification 6-l Operating conditions Parameter Symbol Supply voltage VII0 Operating temperature Topt [Note] Input/Output Signal Name I/O TEST1 I TEST0 0 fi-2 Electrical Parameter terminal
min 4.5 -30
typ 5.0 -
max 5.5
t85
Unit v
"C
of TESTI, TEST0 should be used under the Used condition Fixed H level Connected GNDby O.l,v capacitor
lowing conditions.
characteristics I Svmbl
IOutput "Low" voltage
IOutput "High" voltage j
IOutput "Low" voltage __.---- ! jOutput n--.r High -voltage Output"Low" voltage / lOutput "High" voltage -IOutput "Low" voltage / bms--;;i tagyi-Jutput "Low" voltage I ~_---.
VOM
#l:
Applied to input pins (ICU) and Bidirecional
input mode
pins (OSCB, IOCUZM,IOCURZ)
Applied Applied Applied Applied (OSCO: Applied Applied Applied Applied Applied Applied
to input pins (ICS) to input pins (ICS) and Ridirecional pin (OSCB) input mode to input pins (ICUJ and Bidirecional pins (IOCU2M, IOCURZ) input mode to output pin (OSCO) under the condition the input level of OSCB (input mode) = VDD OV 1 or to output pin (02M) and Bidirecional pin (IOCUZM) output mode to output pins (OlM, TOlM) to output pins (ORZ) and Bidirecional pins (IOCURZ) output mode to output pins (ORZx2) to Bidirecional pin (OSCB)output mode to output pin (TOtM)
SHARP
7. Condition for signal input 7-l In case of using PLL circuit Clock input : OSCI Symbo 1 Parameter Input frequency l/To Duty ratio TOL~M
LZSGjF16
7
(CLKC=H) min
40160
UP 9.4
so/50
max
60140
unit MHZ
%
remarks
Composite (Horizontal) sync. signal (Positive) Input condition Baseon NTSC(M) system Base on PUB, 3) system
: SW1
remarks NTPC=H NTPC=L
fsm125a f &304
600 I 16
~MZ kIi!?l
PS
NTPC=H NTPC=L (Note11
58
PS
Timing of VIN input to be specified. (See fig. 2-h) fsyn=SYNI (composite sync. signal) input frequency (unit : kHz) (Note31 (Note41 In case of no VIN input, vertical counter inside of IC is reset automatically based on f&284 (NTPC=H), fsun/344 (NTPC=L). After VSYfalling, VIN input is invalid during the period of 192H(NTPC=H), 227H(NTPC=L).(lH=l/ fm) However, the case of VSYfalling by automatic reset is exceptional.
Input LOWI, RESH RESV and Input VDI, through and integration circuit(Contro1 circuitry example : refernces) with following value(z ,), turning on by or please input the Low level after VDD --___ _____ this period systemreset. Unit 1 min jSymbol--tYP---~~--~.ioo~aax---- ,
i T"
20 ms _J
' SHARP
LZ9GF16
7-2 In case of input outside sync. signal (CLKC=L)
3) Vertical sync. signal (Negative) : VSY min Symbol Parameter 50 Input frequency fv1 1 Pulse width TV1 4) Input signal timing Parameter time EXCL-HSY Data setup time Data hold
HSY -VSY Data setup time Data hold time
VP f&Z62
3 min 25 25
1.0 1.0
max h/258
5
Unit Hz H
remarks
Symbol
hll
typ
max
Unit
remarks
(Note51 (Note61
ns
ns
hOI hz GIOZ
(Note51 (Note61
In case of outside sync. signal input mode, it show EXCLand HSYtiming. In this case HSY input signal is brought at the rising timing of EXCLinput signal. In case of outside sync. signal input mode, it showHSYand VSYtiming. In this case VSYinput signal is brought at the rising timing of HSYinput signal.
SHARI=
LZ9GF16
9
II I I I II I
I r II
II1 II II II
SHARP
LZgGF"16
10
1
SHARP
LZ9GF16
11
1
I
r II
I I I
I
9. Input / Output signal timing chart for above cases
SOO(O)CK : NTPC = H (NTSC mode) OCR
I(NTSC) -O.WAL) I 1
604(O)CK
O(NTSC) 603.6(I'AL)
: NTPC = H (PAL mode)
1 1
HSY
1045(SAMC=ll) 08 (SAMC=I
104.6(SAhlC=H)
I, )
SPD
\
CLD , QPS
-----~,.-.-~ -0.6; f ! .-......." ~-..._......_.-......_.~......~...~: 72 ....~-.."`\ I -0.6 i ! i .,...._ .._ 106 I ---.-..-..... _-66 -..._-_ \ \ ..-... .. `5 5 $ B // . ... ..." ..-.... ..- _._..._ ..__......_...___........-... ---.--.------.-.-----.---i-0.6 ! II2 2 -0.6 1 ! j i -._--. _-^ 72 112
CTR
CLS
---.---.f-
i 1 i
! I
i ( I
: 66 ..l-_l_
I06
FRPT
------
! I .._ -............ .._........._..........__.........~ .-.......__._.__._. .._.__._.._. - _._..__. _ - ..__......" _ - _...._..-._ i.-_... _.._________.._
i ..--...... _-...... -..._...._._.._..._ ...__.-.......-. ..-...........--...-..-....-.. _._ _.-_--..-! .-_._ I_.-_ ____-_,__.__._._._,___
FRPV
i BLKO
i,.- .._.--.._.-........_...._.__..........._. .._..-..-...., SO I _ .._._.. I i \
60
6(NTSC) i I(I'AL) 1 ('
63
'
63
DIS
I Fig.?,-a Horizontal
I ! I i counter timing chart- 1 ( In case of using PLL circuit)
/
OCK
1200(O)CK
1199 I \I / // I I 1 72 174
HSY
I i 78 174
(5
`;
SPD
CLD
III 201
g > 201
GPS
, .-.--_, *i ....__,___..,_. _-__ i I20 .._ .._._.._............. I: .._. \$ ! ! 120
CTR
I
.
,. . 192 /
_ 5 6
//
>(
i -... ..-....__.-_. _.._..._..-._ ..__..___........_...._ .._ .-_........r...- - __....... -__-._-.___ I ..__II__. fws .__.
1168 1 !
------_--_
---_192
CIS
_ -_____. I i __._._ _.._. . .._ _......8'2 -- ._ _. \ 1-" ! \*. I I,. ._,. .._.._... _....-.._..._...... .._ -_. ! I
FRPT
-._.----_..-..
. . _. I28 1. i ..-..........-. _ 166 . z $
FRPV
i i
i ! ,.. .._.... - ..__..........I..~......_._-......~.....-.......,. ..__.__. ..,......____,__., - - -._I I -_______.__._I ! I .._.... .._.....^._. .~....-...._.__...._._.....~~.......,..~__._... _.._ _.._...._.._.. ._._.__.__.__....___." I--_,_,_ -----_i i
i i I i I
82
128 --__--_ ..--.
74 I
74 I
68
DIS
i 1 I
I I i i
5
Fig.2-b
Horizontal counter timing chart-2
( In case of input outside sync. signal akd SAMC = "H " )
SHARP
.
J
LZ9GF16
s
%
i I I I j I !
,.._
_-.-
/ 1 ! / / ! ! I ! !
v \
e hc
g---.-.-.. `(
..a
_..-.. -..-.---.
SHARI=
LZ9GF16
15
-L 1 I i
SHARP
LZ9GF16
'
16
'i
VSY
626H ------- (NTPC-._- H) -= G26H (NTPC = L)
CHK `(NTPC=H) /
106H 2 ----
u
1 ./ 8911 ._~_ `. -__-.--.--..-.._--____ _________ 626Hm-TPC = II) G26H (NTPC = L) . , 1
CHK (NTPC=L)
Expansion of time axis
VSY
1'
I
I
-
HSY
L uuJHluuuuuuhl
--.-.. __--__----.-III I
nH -...--._ -_.-.~-._-
I
/
Uuu
u u u u u Ill
CHK
106H (NTPC = H) 89H (NTPC = L)
nH
Period of invecter okcillate
----Aeriod of invert& not oaciIIate
l
I
I
Fig.2-f
Output signal timing of CHK (Control signal for the backlight PWM brightness control)
VSY
LOW1
`LOW0
Fig.2-g
Output
signal timing of LOW0
HSY
r
VIN
`r
Pig.2-h
Input signal timing of VIN (Using
separated
circuit of vertical
sync. signal)
HSY
I
I
I
I.
I
I
I
SYNI
I
II2 (fligh-impedance state )
I
I
II
PDP Fig.24 Output signal timing of PDP
SHARP
LZ9GF16'
19
-
SHARP
10. Outline dimension
p-o.mTYP.
48-0.33kO.l
SEE DETAI A
P
DETAIL A N CJ,I d,, d +( PKG. BASE PLANE 6 tl 7 ii m 2
/ I
? o -11 I1
I
*
5% /
ME i QFP48-P-1010 DRAWING NO.
!I - Fikt
j TIN-LEAI: #f&t
1~~~7I/t7~-%~\
A9 $$~trrid~lfr,
a
LEAD FINISH i PLATING NOTE Plastic body dimensions of resin. *ia 1 i AA873 UNIT ! mm
do not include
burr

▲Up To Search▲

Price & Availability of LZ9GF16

	To Download LZ9GF16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .